uniCorer's Blog

//`timescale 1ns/1ns;

module D_FF(q,d,clk,reset);
output q;
input d,clk,reset;
reg q;

always@(posedge reset or negedge clk)
if(reset)
	q<=1'b0;
else
    q<=d;
endmodule

	
module T_FF(q,clk,reset);
output q;
input clk,reset;
wire d;
D_FF dff0(q,d,clk,reset);
not n1(d,q);
endmodule


module ripple_carry_counter(q,clk,reset);
output [3:0] q;
input clk,reset;

T_FF tff0(q[0],clk,reset);
T_FF tff1(q[1],q[0],reset);
T_FF tff2(q[2],q[1],reset);
T_FF tff3(q[3],q[2],reset);

endmodule
//
module stimulus;

reg clk;
reg reset;
wire[3:0] q;
ripple_carry_counter r1(q,clk,reset);
initial
	clk=1'b0;
always
	#5 clk=~clk;
	
initial
begin
	reset=1'b1;
	#15 reset=1'b0;
	#180 reset=1'b1;
	#10 reset=1'b0;
	#20 $finish;
end
initial
	$monitor($time," Output q=%d",q);
	
	//$dumpfile("stimulus.dump");
    //$dumpvars(0, stimulus.clk);
	//$dumpvars(1, stimulus.reset);
	//$dumpvars(2, stimulus.q[0]);
	//$dumpvars(3, stimulus.q[1]);
	//$dumpvars(4, stimulus.q[2]);
	//$dumpvars(5, stimulus.q[3]);
	
endmodule	

运行效果，正好是一个脉冲加一。

1.下载iverilog+gtkwave

2.编写如下模块test.v

`timescale 1ns/1ns
module test_clk;

reg clk;

initial clk = 0;

always
begin
        #1000 clk = 1;
        #2000 clk = 0;
        #3000 $finish;
end

initial
begin
        $dumpfile("test.dump");
        $dumpvars(0, clk);
end

endmodule

3.cmd下

D:\>iverilog -o test test.v

D:\>vvp test
VCD info: dumpfile test.dump opened for output.

D:\>gtkwave test.dump

显示gtkwave

4.Append clk信号得到如下图

如此便完成了verilog模块编译与调试功能。